1. Field of the Invention
The present invention generally relates to an output multiplexer (MUX) for a high speed memory and, more particularly, to an output MUX having an output interlock circuit which ensures that only one data signal can be present on the output line at a time regardless of whether or not a control signal for the next data cycle transitions during this same time.
2. Description of the Related Art
Static random access memory (SRAM) is a type of high speed memory wherein each bit is represented by the state of a circuit with two stable states. Such a "bistable" circuit can be built with four transistors (for maximum density) or six (for highest speed and lowest power). SRAM retains data bits in its memory as long as power is being supplied. Unlike dynamic RAM (DRAM), which stores bits in cells made up of a capacitor and a transistor, SRAM does not have to be periodically refreshed. Static RAM provides faster access to data but is more expensive than DRAM. SRAM is commonly used for a computer's level two (L2) cache memory. The function of the L2 cache is to stand between DRAM and a computer's central processing unit (CPU), offering faster access than DRAM.
SRAM memory cells are typically configured in arrays and addressable subarrays. An output multiplexer (MUX) receives the data from the SRAM subarrays and multiplexes the data onto the data bus for the CPU. Unfortunately, due to manufacturing considerations as well as the physical placement within the SRAM array, not all of the subarrays are accessible at the same speed. That is, some of the subarrays are accessible faster and some are slower than others. The array data therefore has non-uniform timing relations as compared to the SRAM clock due to a large skew associated with addressing the fastest and then the slowest subarrays in the memory.
These non-uniform timing relations result in a critical timing bottleneck the becomes more pervasive with the increasing speed of the memory device. This situation leaves a very small window for the MUX control inputs to transition between the reset of the slowest data and prior to the fastest data. Furthermore, it leaves little if any margin to increase frequency (i.e., the faster the frequency the smaller the timing window becomes).